The present inventive concept relates to memory page caches, and more particularly, to a page cache device and method for efficient memory page mapping.
Today, most operating system (OS) kernels or hypervisors utilize parts of dynamic random access memory (DRAM) as a page cache for frequently-used, volatile user data, file system data, and so forth. Because DRAM is significantly more expensive than negative-AND (NAND) memory, most data center servers have limited amounts of DRAM, for cost considerations.
Some applications, particularly big data applications, can benefit from having a much larger working set stored in a DRAM page cache. When the application working set exceeds the amount of DRAM available for page caching, the kernel and hypervisor (hereinafter referred to as kernel for both) uses a least recently used (LRU), or similar, replacement policy to evict cache pages from DRAM to secondary storage. Because the secondary storage is much slower than DRAM (e.g., more than 100 times slower), there is significant overhead in dealing with the disparity between DRAM and secondary storage access speed. As storage or memory devices, both volatile and non-volatile, become faster, the processing complexity overhead incurred becomes a significant processing cost factor.
Conventional memory page mapping techniques require a complex host interface and are inefficient in mapping huge virtual address spaces to size-limited physical address spaces. As demand for large memory address spaces continues to increase with time, the problems with cost and efficiency will continue to persist and even get worse.
Moreover, when a kernel normally works with a storage device, a kernel block layer is invoked to process all input/output (IO)-related requests. The kernel storage layers are subsequently called to forward the request to the IO device's device driver. This processing path is complicated and difficult to achieve high IO device performance for the most frequent JO request patterns. When the IO request patterns change, the processing path must also change, otherwise a performance penalty is incurred. Embodiments of the present inventive concept address these and other limitations in the prior art.